US 12,406,727 B2
Memory device
Yu Shimada, Fujisawa Kanagawa (JP); Ryousuke Takizawa, Naka Kanagawa (JP); and Akira Katayama, Yokohama Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Sep. 1, 2023, as Appl. No. 18/460,493.
Claims priority of application No. 2022-151313 (JP), filed on Sep. 22, 2022.
Prior Publication US 2024/0112732 A1, Apr. 4, 2024
Int. Cl. G11C 13/00 (2006.01)
CPC G11C 13/0069 (2013.01) [G11C 13/0038 (2013.01); G11C 13/004 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory cell connected between a first signal line and a second signal line;
a first wiring connected to the first signal line via a first switch;
a second wiring connected to the second signal line via a second switch; and
a first precharging circuit connected to the first wiring,
wherein, during a write sequence for the memory cell,
the first precharging circuit charges the first signal line and the first wiring which are connected via the first switch in an on state,
the memory cell is activated according to a voltage difference between the first signal line and the second signal line, and
a write current generated from the charged first signal line and the charged first wiring flows from the first wiring to the second wiring via the activated memory cell.