US 12,406,725 B2
Self-selecting memory device, memory system having the same, and operating method thereof
Soyeon Choi, Suwon-si (KR); Zhe Wu, Suwon-si (KR); Chungman Kim, Suwon-si (KR); Seunggeun Yu, Suwon-si (KR); and Jabin Lee, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jun. 14, 2023, as Appl. No. 18/334,790.
Claims priority of application No. 10-2022-0161605 (KR), filed on Nov. 28, 2022.
Prior Publication US 2024/0177771 A1, May 30, 2024
Int. Cl. G11C 13/00 (2006.01)
CPC G11C 13/0069 (2013.01) [G11C 13/0004 (2013.01); G11C 13/004 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An operating method of a self-selecting memory device, comprising
applying a first write pulse corresponding to a first state to a first memory cell during a first pulse width; and
applying a second write pulse corresponding to a second state to a second memory cell during a second pulse width,
wherein the first write pulse and the second write pulse have substantially opposite polarities,
wherein the first pulse width is longer than the second pulse width,
wherein each of the first memory cell and the second memory cell comprises:
a lower electrode;
a first chalcogenide layer disposed above the lower electrode;
an intermediate electrode disposed above the first chalcogenide layer;
a second chalcogenide layer disposed above the intermediate electrode; and
an upper electrode disposed above the second chalcogenide layer,
wherein one of the first chalcogenide layer and the second chalcogenide layer includes a storage material, and the other of the first chalcogenide layer and the second chalcogenide layer includes a selection material, and
wherein the first chalcogenide layer is in direct contact with the lower electrode and the intermediate electrode, and the second chalcogenide layer is in direct contact with the intermediate electrode and the upper electrode.