| CPC G11C 13/003 (2013.01) [G11C 13/004 (2013.01); G11C 2213/79 (2013.01)] | 20 Claims |
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1. An apparatus, comprising:
a plurality of bit lines intersecting with a plurality of word lines;
a plurality of cross-point devices, wherein each of the plurality of cross-point devices is connected to at least one of the plurality of word lines and at least one of the plurality of bit lines, and wherein each of the plurality of cross-point devices comprises a resistive random-access memory (RRAM) device; and
a plurality of sensing circuits configured to:
amplify a plurality of bit line voltages settled on the plurality of bit lines in response to an application of a plurality of input voltages to the plurality of cross-point devices via the plurality of word lines; and
generate a plurality of digital outputs representative of the amplified bit line voltages.
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