US 12,406,722 B2
Integrated circuit device including an SRAM portion having end power select circuits
Darryl G. Walker, San Jose, CA (US)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Mar. 1, 2024, as Appl. No. 18/592,833.
Application 18/592,833 is a continuation of application No. 17/738,321, filed on May 6, 2022, granted, now 11,955,171.
Claims priority of provisional application 63/244,442, filed on Sep. 15, 2021.
Prior Publication US 2024/0203489 A1, Jun. 20, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/00 (2006.01); G11C 11/412 (2006.01); G11C 11/418 (2006.01); G11C 11/419 (2006.01)
CPC G11C 11/419 (2013.01) [G11C 11/412 (2013.01); G11C 11/418 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of operating an integrated circuit device including the steps of:
enabling a power control circuit to provide power control signals according to at least one row address signal when an assist enable signal has an assist enable logic level and the integrated circuit device is in a write mode of operation wherein data is written to at least one selected SRAM memory cell; and
selectively controlling at least one impedance path between a power supply potential and an array power line electrically connected to provide power to the at least one selected SRAM memory cell in a memory array in response to the at least one power control signal,
wherein each at least one impedance path between the power supply potential and the array power line includes a plurality of channels between a source terminal and a drain terminal of an insulated gate field effect transistor (IGFET), the plurality of channels disposed in a first direction and substantially aligned in a second direction substantially perpendicular to the first direction and having a control gate structure that contiguously surrounds the plurality of channels.