US 12,406,721 B2
Memory cell
Chih-Sheng Lin, Tainan (TW); Tuo-Hung Hou, Hsinchu (TW); Fu-Cheng Tsai, Tainan (TW); Jian-Wei Su, Hsinchu (TW); and Kuo-Hua Tseng, Yilan County (TW)
Assigned to Industrial Technology Research Institute, Hsinchu (TW)
Filed by Industrial Technology Research Institute, Hsinchu (TW)
Filed on Nov. 8, 2022, as Appl. No. 17/983,331.
Claims priority of application No. 111133890 (TW), filed on Sep. 7, 2022.
Prior Publication US 2024/0079051 A1, Mar. 7, 2024
Int. Cl. G11C 11/41 (2006.01); G11C 11/412 (2006.01); G11C 11/418 (2006.01)
CPC G11C 11/412 (2013.01) [G11C 11/418 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory cell, comprising:
a first transistor, having a first terminal coupled to a bit line;
a second transistor, having a first terminal coupled to a bit line bar;
a weight storage circuit, coupled between a gate terminal of the first transistor and a gate terminal of the second transistor, and configured to store a weight value; and
a driving circuit, coupled to a second terminal of the first transistor, a second terminal of the second transistor, and at least one word line, and configured to receive at least one threshold voltage and receive at least one input data from the word line,
wherein the weight storage circuit determines to turn on the first transistor or the second transistor according to output values of a storage node and a storage node bar of the weight storage circuit, the driving circuit determines whether to generate an operation current on a path of the turned-on first transistor or the turned-on second transistor according to the threshold voltage and the input data.