| CPC G11C 11/4096 (2013.01) [G11C 11/4094 (2013.01); H10B 12/05 (2023.02); H10B 12/482 (2023.02)] | 20 Claims |
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1. A memory structure, comprising:
a plurality of insulating layers and a plurality of gate layers that are alternately stacked;
a first doping layer penetrating through the insulating layers and the gate layers;
a plurality of channel layers respectively connected to the first doping layer, wherein the channel layers and the insulating layers are alternately stacked;
a columnar channel penetrating through the insulating layers and the gate layers;
a plurality of second doping layers respectively surrounding the columnar channel, wherein the second doping layers are respectively connected to the channel layers;
a third doping layer coupled to the columnar channel;
a fourth doping layer coupled to the columnar channel;
a first dielectric layer disposed between the first doping layer and the gate layers;
a plurality of second dielectric layers respectively disposed between the second doping layers and the gate layers;
a third dielectric layer disposed between the columnar channel and the second doping layers; and
a plurality of fourth dielectric layers respectively disposed between the channel layers and the gate layers.
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