US 12,406,719 B2
Storage and accessing methods for parameters in streaming AI accelerator chip
Chenglong Zeng, Guangdong (CN); Kuen Hung Tsoi, Guangdong (CN); and Xinyu Niu, Guangdong (CN)
Assigned to Shenzhen Corerain Technologies Co., Ltd., Shenzhen (CN)
Filed by Shenzhen Corerain Technologies Co., Ltd., Guangdong (CN)
Filed on Mar. 16, 2023, as Appl. No. 18/184,686.
Claims priority of application No. 202210294078.3 (CN), filed on Mar. 24, 2022.
Prior Publication US 2023/0307036 A1, Sep. 28, 2023
Int. Cl. G11C 11/4093 (2006.01); G11C 11/4096 (2006.01); G11C 11/54 (2006.01)
CPC G11C 11/4093 (2013.01) [G11C 11/4096 (2013.01); G11C 11/54 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A streaming-based data buffer comprising:
a plurality of banks, different banks being configured to store different data;
a data read circuit configured to receive a read control signal and a read address corresponding to a computation task, in the case the read control signal corresponds to a first read mode, determine n banks from the plurality of banks based on the read control signal, and read a first data required for performing the computation task in parallel from the n banks based on the read address, the first data comprising n pieces of data corresponding to the n banks in a one-to-one correspondence, n≥2, n being a positive integer;
wherein the read address comprises an addressing address and a chip select address, the data read circuit is configured to read the first data based on the addressing address;
the data read circuit is further configured to, in the case the read control signal corresponds to a second read mode, determine one bank from the plurality of banks based on the chip select address and read a second data required for performing the computation task from the one bank based on the addressing address; and
the read control signal corresponds to the second read mode in the case the computation task is a bilinear interpolation in the neural network algorithm.