US 12,406,718 B2
Processing in memory
Perry V. Lea, Eagle, ID (US); and Timothy P. Finkbeiner, Boise, ID (US)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on Feb. 1, 2024, as Appl. No. 18/430,136.
Application 16/989,620 is a division of application No. 15/693,366, filed on Aug. 31, 2017, granted, now 10,741,239, issued on Aug. 11, 2020.
Application 18/430,136 is a continuation of application No. 17/694,184, filed on Mar. 14, 2022, granted, now 11,894,045.
Application 17/694,184 is a continuation of application No. 16/989,620, filed on Aug. 10, 2020, granted, now 11,276,457, issued on Mar. 15, 2022.
Prior Publication US 2024/0170047 A1, May 23, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/408 (2006.01); G06F 3/06 (2006.01); G11C 7/10 (2006.01); G11C 11/4076 (2006.01); G11C 11/4091 (2006.01); G11C 11/4096 (2006.01)
CPC G11C 11/4085 (2013.01) [G06F 3/061 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G11C 7/1006 (2013.01); G11C 11/4076 (2013.01); G11C 11/408 (2013.01); G11C 11/4091 (2013.01); G06F 3/0625 (2013.01); G11C 11/4096 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a memory device configured to perform bit vector operations; and
a host comprising:
control logic configured to generate high level instructions associated with the bit vector operations;
a sequencer configured to decode the high level instructions into a plurality of low level instructions associated with the bit vector operations; and
timing circuitry configured to control timing, associated with the plurality of low level instructions associated with the bit vector operations, of performance of a compute operation;
wherein the plurality of low level instructions are executable in parallel by a plurality of compute components downstream from the sequencer.