US 12,406,717 B2
Apparatuses and methods for dynamically allocated aggressor detection
Sujeet Ayyapureddi, Boise, ID (US); and Donald M. Morgan, Meridian, ID (US)
Assigned to MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Sep. 14, 2022, as Appl. No. 17/932,206.
Application 17/932,206 is a continuation of application No. 17/153,555, filed on Jan. 20, 2021, granted, now 11,482,275.
Prior Publication US 2023/0010619 A1, Jan. 12, 2023
Int. Cl. G11C 11/4078 (2006.01); G11C 11/406 (2006.01); G11C 11/408 (2006.01)
CPC G11C 11/4078 (2013.01) [G11C 11/406 (2013.01); G11C 11/4085 (2013.01); G11C 11/4087 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a plurality of memory banks, each comprising a plurality of word lines; and
an aggressor detector circuit configured to receive a bank address associated with one of the plurality of memory banks and a row address associated with one of the plurality of word lines in that bank and determine if the one of the plurality of word lines is an aggressor based on the row address and the bank address,
wherein the aggressor detector circuit is configured to determine if the row address and the bank address are associated with the aggressor word line based on a comparison of the row address and the bank address to a stored row address and a stored bank address.