US 12,406,716 B2
Refresh operations in embedded dynamic random access memories (DRAMs)
Nihaar N. Mahatme, Austin, TX (US); Anirban Roy, Austin, TX (US); and Uzi Zangi, Hod-Hasharon (IL)
Assigned to NXP USA, Inc., Austin, TX (US)
Filed by NXP USA, Inc., Austin, TX (US)
Filed on Dec. 5, 2023, as Appl. No. 18/529,175.
Prior Publication US 2025/0182807 A1, Jun. 5, 2025
Int. Cl. G11C 11/40 (2006.01); G11C 11/406 (2006.01)
CPC G11C 11/40603 (2013.01) 20 Claims
OG exemplary drawing
 
1. A data processing system, comprising:
a dynamic random access memory (DRAM) having a plurality of DRAM cells, each with a capacitive storage element;
a prefetcher coupled to the DRAM and configured to prefetch information from the DRAM into a prefetch buffer in accordance with a prefetch pattern of addresses in the DRAM; and
a refresh controller coupled to the DRAM, the refresh controller comprising a dynamic refresh control circuit coupled to the prefetcher and configured to:
detect prefetch patterns of the prefetcher, and
in response to a detected prefetch pattern, refresh locations of the DRAM in accordance with a refresh pattern of addresses which is based on the prefetch pattern of addresses.