| CPC G11C 11/406 (2013.01) | 24 Claims |

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1. A memory device comprising:
a row-hammer tracking circuit configured to:
generate short interval signals each having one of first to n-th lengths based on input intervals between active commands, and
generate a rate control signal based on whether a pattern of the short interval signals corresponds to a row-hammer attack pattern; and
a target command issue circuit configured to adjust a frequency of a target refresh operation according to the rate control signal.
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