US 12,406,713 B2
Probabilistic computing devices based on stochastic switching in a ferroelectric field-effect transistor
Punyashloka Debashis, Hillsboro, OR (US); Dmitri Evgenievich Nikonov, Beaverton, OR (US); Hai Li, Portland, OR (US); Chia-Ching Lin, Portland, OR (US); Raseong Kim, Portland, OR (US); Tanay A. Gosavi, Portland, OR (US); Ashish Verma Penumatcha, Beaverton, OR (US); Uygar E. Avci, Portland, OR (US); Marko Radosavljevic, Portland, OR (US); and Ian Alexander Young, Olympia, WA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Aug. 23, 2021, as Appl. No. 17/409,483.
Prior Publication US 2023/0058938 A1, Feb. 23, 2023
Int. Cl. G11C 11/22 (2006.01); H10B 51/30 (2023.01)
CPC G11C 11/2275 (2013.01) [G11C 11/223 (2013.01); G11C 11/2273 (2013.01); H10B 51/30 (2023.02); G11C 11/2293 (2013.01)] 24 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first field-effect transistor (FET) comprising:
a source region;
a drain region;
a source electrode on the source region;
a drain electrode on the drain region;
a channel region between the source and drain regions;
a dielectric layer on a surface over the channel region;
an electrode layer above the dielectric layer; and
a ferroelectric (FE) material layer between the dielectric layer and the electrode layer;
a second FET comprising a source electrode, a drain electrode, and a gate electrode, wherein the drain electrode of the second FET is connected to the drain electrode of the first FET; and
a D flip-flop circuit connected to the drain electrode of the first FET and the drain electrode of the second FET.