US 12,406,712 B2
Sensing scheme for a memory with shared sense components
Yuan He, Boise, ID (US); Tae H. Kim, Boise, ID (US); and Scott James Derner, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 19, 2024, as Appl. No. 18/581,260.
Application 18/581,260 is a continuation of application No. 18/048,738, filed on Oct. 21, 2022, granted, now 11,915,735.
Application 18/048,738 is a continuation of application No. 17/171,873, filed on Feb. 9, 2021, granted, now 11,501,815, issued on Nov. 15, 2022.
Prior Publication US 2024/0274180 A1, Aug. 15, 2024
Int. Cl. G11C 11/22 (2006.01)
CPC G11C 11/2273 (2013.01) [G11C 11/221 (2013.01); G11C 11/2255 (2013.01); G11C 11/2257 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a first switching component configured to couple a first digit line of a first memory cell, in a first tier of memory cells, with an input of a first sense component;
a second switching component configured to couple a second digit line of a second memory cell, in a second tier of memory cells, with an input of a second sense component, the second memory cell coupled with a same word line as the first memory cell and coupled with a same plate line as the first memory cell;
the first sense component configured to sense the first memory cell based at least in part on the first switching component coupling the first digit line with the input of the first sense component; and
the second sense component configured to sense, concurrently with the first sense component sensing the first memory cell, the second memory cell based at least in part on the second switching component coupling the second digit line with the input of the second sense component.