| CPC G11C 11/1675 (2013.01) [G11C 11/1655 (2013.01); G11C 11/1673 (2013.01); G11C 11/1697 (2013.01)] | 20 Claims |
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1. A circuit with a logical function of a computing-in-memory (CiM) operation, comprising:
a first switch, coupled to a read bit line and controlled by a first input data;
a second switch, coupled to the read bit line and controlled by an inverted first input data, wherein the inverted first input data is an inverted signal of the first input data;
a first spin-orbit torque (SOT) magneto-resistive random-access memory (MRAM) cell, a bit-line node of the first SOT MRAM cell is coupled to the first switch, the first SOT MRAM cell has a first current path for setting a state of the first SOT MRAM cell;
a second SOT MRAM cell, a bit-line node of the second SOT MRAM cell is coupled to the second switch, the second SOT MRAM cell has a second current path for setting a state of the second SOT MRAM cell, one terminal of the first current path and one terminal of the second current path are coupled to a predetermined voltage terminal; and
a third switch, coupled to a write bit line corresponding to a second input data, the other terminal of the first current path, and one terminal of the second current path, and the third switch is controlled by a write word line,
wherein in response to the third switch is turned-on according to the write word line, a current produced by a voltage of the write bit line corresponding to the second input data and a predetermined voltage of the predetermined voltage terminal is split to flow through the first current path and the second current path to set the states of the first SOT MRAM cell and the second SOT MRAM cell at the same time, the state of the first SOT MRAM cell is different from the state of the second SOT MRAM cell, and,
one of the state of the first SOT MRAM cell and the state of the second SOT MRAM cell is read according to one of the inverted first input data and the first input data.
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