| CPC G11C 11/1659 (2013.01) [G11C 11/161 (2013.01)] | 15 Claims |
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1. A forming method performed on a memory device, the memory device including a plurality of first interconnects in a first direction, a plurality of second interconnects in a second direction intersecting the first direction, and a plurality of memory cells, each of the plurality of memory cells being associated with a set of one of the plurality of first interconnects and one of the plurality of second interconnects between the plurality of first interconnects and the plurality of second interconnects and including a variable resistance element and a switching element which are coupled in series, and the forming method comprising:
selecting a memory cell having a highest interconnect resistance from among memory cells of the plurality of memory cells on which a forming process has not been performed;
performing the forming process on the switching element included in the selected memory cell; and
repeating the selecting and the performing on the plurality of memory cells,
wherein the forming process is a process for changing current-voltage characteristics of the switching element.
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