| CPC G11C 11/161 (2013.01) [G11C 5/06 (2013.01); G11C 11/1659 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); G11C 11/1697 (2013.01)] | 20 Claims |

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1. A method of forming an integrated chip, comprising:
forming a first memory array over a substrate and comprising a first plurality of memory cells arranged in rows and columns, wherein the first plurality of memory cells respectively comprises a unipolar selector and a data-storage element electrically coupled in series with a current path across the data-storage element in one way, wherein the data-storage element is configured to be set from a first data state to a second data state by applying a writing voltage across the data-storage element;
forming a first plurality of bit lines extending along corresponding rows of first the memory array and respectively connected to first terminals of the first plurality of memory cells in the corresponding rows;
forming a first plurality of source lines extending along corresponding columns of the first memory array and respectively connected to second terminals of the first plurality of memory cells in the corresponding columns; and
forming a magnetic field generator coupled to the first memory array and configured to generate an external magnetic field to set the data-storage element to the first data state.
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