US 12,406,707 B2
Method of managing memory in an integrated circuit card and corresponding integrated circuit card
Amedeo Veneroso, Caserta (IT); and Carlo Cimino, Naples (IT)
Assigned to STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed by STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed on Apr. 4, 2023, as Appl. No. 18/295,558.
Claims priority of application No. 102022000007676 (IT), filed on Apr. 15, 2022.
Prior Publication US 2023/0335169 A1, Oct. 19, 2023
Int. Cl. G11C 16/06 (2006.01); G11C 8/04 (2006.01); G11C 8/16 (2006.01)
CPC G11C 8/04 (2013.01) [G11C 8/16 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of managing memory in an integrated circuit card having a non-volatile memory portion and a random access memory (RAM) memory portion, the method comprising:
creating, in a non-volatile memory heap in the non-volatile memory portion, one or more array pointers corresponding to respective one or more transient arrays to be allocated in the RAM memory portion, each array pointer comprising a transient array size and a transient array address, each transient array address being a logical or indirect address pointing indirectly to an area of the RAM memory portion in which a respective transient array is to be allocated; and
assigning, in the RAM memory portion, memory only to non-zero transient arrays having at least one value different from zero.