US 12,406,705 B2
In-memory computation circuit using static random access memory (SRAM) array segmentation
Harsh Rawat, Faridabad (IN); Kedar Janardan Dhori, Ghaziabad (IN); Promod Kumar, Greater Noida (IN); Nitin Chawla, Noida (IN); and Manuj Ayodhyawasi, Noida (IN)
Assigned to STMicroelectronics International N.V., Geneva (CH)
Filed by STMicroelectronics International N.V., Geneva (CH)
Filed on Apr. 19, 2023, as Appl. No. 18/136,491.
Claims priority of provisional application 63/345,483, filed on May 25, 2022.
Prior Publication US 2023/0410862 A1, Dec. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/16 (2006.01); G11C 7/12 (2006.01); G11C 8/08 (2006.01)
CPC G11C 7/16 (2013.01) [G11C 7/12 (2013.01); G11C 8/08 (2013.01)] 24 Claims
OG exemplary drawing
 
1. An in-memory computation circuit, comprising:
a memory array including a plurality of sub-arrays, wherein each sub-array includes memory cells arranged in a matrix with plural rows and plural columns, each row including a word line connected to the memory cells of the row, and each column including a local bit line connected to the memory cells of the column, said memory cells configured to store bits of weight data for an in-memory compute operation;
a word line driver circuit for each row having an output connected to drive the word line of the row;
a row controller circuit configured to simultaneously actuate only one word line per sub-array for the in-memory compute operation by applying pulses through the word line driver circuits to the word lines; and
a plurality of global bit lines, where each global bit line is capacitively coupled to a plurality of local bit lines.