US 12,406,704 B2
Multi-stage bit line pre-charge
Wei-Cheng Wu, Hsinchu (TW); Kao-Cheng Lin, Taipei (TW); Chih-Cheng Yu, Hsinchu (TW); Pei-Yuan Li, Hsinchu (TW); Chien-Chen Lin, Kaohsiung (TW); Wei Min Chan, Taipei (TW); and Yen-Huei Chen, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Jul. 26, 2023, as Appl. No. 18/359,079.
Application 18/359,079 is a continuation of application No. 17/408,567, filed on Aug. 23, 2021, granted, now 11,749,321.
Application 17/408,567 is a continuation of application No. 16/785,875, filed on Feb. 10, 2020, granted, now 11,100,964, issued on Aug. 24, 2021.
Prior Publication US 2024/0029769 A1, Jan. 25, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/12 (2006.01); G11C 7/10 (2006.01); G11C 11/4076 (2006.01); G11C 11/4091 (2006.01); G11C 11/4093 (2006.01); G11C 11/4094 (2006.01); G11C 11/4096 (2006.01); G11C 11/413 (2006.01); G11C 11/416 (2006.01); G11C 11/419 (2006.01)
CPC G11C 7/12 (2013.01) [G11C 7/1048 (2013.01); G11C 11/4076 (2013.01); G11C 11/4091 (2013.01); G11C 11/4093 (2013.01); G11C 11/4094 (2013.01); G11C 11/4096 (2013.01); G11C 11/413 (2013.01); G11C 11/416 (2013.01); G11C 11/419 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit comprising:
a bit cell responsive to a bit line and a bit line bar;
a pre-charge circuit including:
a first pre-charge component configured to charge the bit line and the bit line bar prior to conclusion of a read operation; and
a second pre-charge component configured to charge the bit line and the bit line bar at the end of the read operation, wherein:
the first pre-charge component of the pre-charge circuit includes a first transistor and a second transistor;
the first transistor has a gate terminal configured to receive a first control signal and a source/drain terminal connected to a first source/drain terminal of the second transistor; and
the second transistor has a gate terminal and a second source/drain terminal connected to each other and to both the bit line and the bit line bar; and
a pre-charge control circuit configured to provide the first control signal to the first pre-charge component and a second control signal to the second pre-charge component, wherein:
the first control signal is transitioned from inhibiting charging to enable charging by the first pre-charging component prior to deactivation of a word line; and
the second control signal is transitioned to from inhibiting charging to enable charging by the second pre-charge component after transitioning of the first control signal.