US 12,406,702 B2
Switches to reduce routing rails of memory system
Meng-Sheng Chang, Chu-bei (TW); Chia-En Huang, Xinfeng Township (TW); Yi-Ching Liu, Hsinchu (TW); and Yih Wang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 3, 2024, as Appl. No. 18/763,048.
Application 18/763,048 is a continuation of application No. 18/361,542, filed on Jul. 28, 2023, granted, now 12,062,408.
Application 18/361,542 is a continuation of application No. 17/460,215, filed on Aug. 28, 2021, granted, now 11,756,591.
Prior Publication US 2024/0355364 A1, Oct. 24, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 8/12 (2006.01); G11C 5/06 (2006.01)
CPC G11C 5/063 (2013.01) 20 Claims
OG exemplary drawing
 
1. A method, comprising:
providing a first set of memory cells by:
connecting a first subset of memory cells between a first local bit line and a first local select line; and
connecting a second subset of memory cells between a second local bit line and a second local select line;
connecting a first switch between the first local bit line and a first global bit line;
connecting a second switch between the second local bit line and the first global bit line;
providing a second set of memory cells by:
connecting a third subset of memory cells between a third local bit line and a third local select line; and
connecting a fourth subset of memory cells between a fourth local bit line and a fourth local select line;
connecting a third switch between the third local bit line and a second global bit line;
connecting a fourth switch between the fourth local bit line and the second global bit line;
connecting a gate electrode of a first memory cell of the first subset of memory cells to a gate electrode of a second memory cell of the second subset of memory cells through a first local word line; and
connecting a gate electrode of a third memory cell of the first subset of memory cells to a gate electrode of a fourth memory cell of the second subset of memory cells through a second local word line.