US 12,406,701 B2
Memory component for a system-on-chip device
Alberto Troia, Munich (DE); and Antonino Mondello, Messina (IT)
Filed by Lodestar Licensing Group, LLC, Evanston, IL (US)
Filed on Jul. 28, 2023, as Appl. No. 18/227,727.
Application 18/227,727 is a continuation of application No. 17/745,583, filed on May 16, 2022, granted, now 11,715,498.
Application 17/745,583 is a continuation of application No. 16/624,438, granted, now 11,335,383, issued on May 17, 2022, previously published as PCT/IB2019/000484, filed on May 31, 2019.
Prior Publication US 2024/0071424 A1, Feb. 29, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 5/04 (2006.01); G11C 5/02 (2006.01); G11C 5/06 (2006.01)
CPC G11C 5/025 (2013.01) [G11C 5/04 (2013.01); G11C 5/06 (2013.01); G11C 2207/105 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a System-on-Chip (SoC) structure; and
a memory component comprising:
a controller coupled to a memory array; and
a surface including a plurality of interconnection pads located thereon; and
wherein the SoC structure and an overlapping portion of the memory component are coupled through connection pillars corresponding to the plurality of interconnection pads via a logic over pads technology.