| CPC G09G 3/32 (2013.01) [G09G 3/3266 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0291 (2013.01)] | 20 Claims |
|
1. A gate driving circuit, comprising:
a scan output buffer configured to output a first scan signal to a scan output node electrically connected to a first scan signal line among a plurality of scan signal lines disposed on a display panel, and including a scan pull-up transistor and a scan pull-down transistor; and
a control circuit configured to control the scan output buffer, wherein the control circuit includes a first control node and a second control node and includes an inverter circuit configured to charge or discharge a QB node,
wherein the inverter circuit includes:
a first transistor configured to control a connection between a high-potential node and the QB node;
a second transistor configured to control a connection between the QB node and a low-potential node;
a third transistor configured to control a connection between the high-potential node and the first control node;
a fourth transistor configured to control a connection between the second control node and the low-potential node; and
a fifth transistor configured to control a connection between the first control node and the second control node,
wherein a gate node of the first transistor is electrically connected to the first control node, a gate node of the second transistor is electrically connected to a Q node, and a gate node of the fourth transistor is electrically connected to the Q node, and
wherein a first electrode of the fifth transistor is physically and electrically connected to the first control node and the gate node of the first transistor, a second electrode of the fifth transistor is physically and electrically connected to a first electrode of the fourth transistor, and a second electrode of the fourth transistor is directly connected to the low-potential node directly connected to any one of first and second electrodes of the second transistor.
|