US 12,406,612 B2
Shift register unit, driving circuit and display device
Can Zheng, Beijing (CN)
Assigned to BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed by BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed on Jul. 9, 2024, as Appl. No. 18/767,335.
Application 18/767,335 is a continuation of application No. 18/336,565, filed on Jun. 16, 2023, granted, now 12,073,765.
Application 18/336,565 is a continuation of application No. 18/092,974, filed on Jan. 4, 2023, granted, now 11,854,460, issued on Dec. 26, 2023.
Application 18/092,974 is a continuation of application No. 17/696,251, filed on Mar. 16, 2022, granted, now 11,574,581, issued on Feb. 7, 2023.
Application 17/696,251 is a continuation of application No. 16/642,140, granted, now 11,308,854, issued on Apr. 19, 2022, previously published as PCT/CN2019/079171, filed on Mar. 22, 2019.
Prior Publication US 2024/0363051 A1, Oct. 31, 2024
Int. Cl. G09G 3/20 (2006.01)
CPC G09G 3/2092 (2013.01) [G09G 2310/0286 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A shift register unit, comprising a first input circuit, a second input circuit, an output circuit, a first control circuit, a second control circuit and an output reset circuit,
wherein the first input circuit is electrically connected to a first node, and is configured to transmit an input signal to the first node under control of a first clock signal;
the second input circuit is electrically connected to the first node and a second node, and is configured to control a level of the second node under control of a level of the first node or the first clock signal and receive a first low voltage from a first low voltage signal line;
the first control circuit is electrically connected to the second node and a third node, and is configured to control a level of the third node under control of the level of the second node and a second clock signal;
the output circuit is electrically connected to the third node, a second voltage signal line and an output terminal, and is configured to output an output signal to the output terminal under control of the level of the third node;
the second control circuit is electrically connected to the first node, the third node and a first voltage signal line, and is configured to control the level of the third node under control of the level of the first node, and
the output reset circuit is electrically connected to the first node and the output terminal, and is configured to receive a second low voltage from a second low voltage signal line,
wherein the second low voltage signal line and the first low voltage signal line are two different voltage signal lines.