| CPC G09G 3/2092 (2013.01) [G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G11C 19/287 (2013.01)] | 14 Claims |
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1. A shift register, comprising:
a first input unit coupled to a first node and configured to write a signal into the first node;
a first output unit, comprising:
a control terminal coupled to the first node,
a first terminal configured to receive a first voltage signal, and
a second terminal coupled to a signal output terminal;
a second input unit coupled to a second node and configured to write a signal into the second node;
a second output unit, comprising:
a control terminal coupled to the second node,
a first terminal configured to receive a first clock signal, and
a second terminal coupled to the signal output terminal; and
a holding unit comprising an output terminal coupled to the second node, and configured to maintain a potential of the second node at least during a period when the first output unit is off and the second output unit is on,
wherein the holding unit comprises:
a first subunit, comprising:
an output terminal coupled to a third node; and
a first transistor, comprising:
a control terminal configured to receive the first clock signal,
a first terminal of the first transistor coupled to the third node, and
a second terminal of the first transistor coupled to the second node;
wherein during the period when the first output unit is off and the second output unit is on, the first subunit inputs a second voltage signal to the third node, and when the first transistor is turned on, the first transistor writes the second voltage signal into the second node to maintain the potential of the second node.
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