US 12,406,610 B2
Display substrate, driving method therefor, and display apparatus
Benlian Wang, Beijing (CN); Yudiao Cheng, Beijing (CN); Zhenhua Zhang, Beijing (CN); and Yuxin Zhang, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 18/563,556
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed May 24, 2021, PCT No. PCT/CN2021/095575
§ 371(c)(1), (2) Date Nov. 22, 2023,
PCT Pub. No. WO2022/246610, PCT Pub. Date Dec. 1, 2022.
Prior Publication US 2024/0221590 A1, Jul. 4, 2024
Int. Cl. G09G 3/30 (2006.01); G09G 3/20 (2006.01)
CPC G09G 3/2092 (2013.01) [G09G 2300/0426 (2013.01); G09G 2300/0452 (2013.01); G09G 2300/0842 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A display substrate, having a display area and a bezel area, wherein the display area comprises a first display area and a second display area; the first display area has a light transmittance higher than a light transmittance of the second display area;
the first display area comprises a plurality of pixel units distributed in an array, each of the plurality of pixel units comprising a first subpixel and a second subpixel emitting different colors of light; and
the first display area comprises a first initialization voltage line and a second initialization voltage line, wherein the first initialization voltage line is electrically connected to the first subpixel, the second initialization voltage line is electrically connected to the second subpixel, and the first initialization voltage line and the second initialization voltage line are configured to receive different initialization voltages,
wherein the pixel unit further comprises a third subpixel emitting light of a color different from the colors of both the first subpixel and the second subpixel, and the third subpixel is electrically connected to the second initialization voltage line,
wherein the display substrate comprises a base substrate, a first gate metal layer, a second gate metal layer, and a source/drain metal layer which are sequentially stacked;
wherein the first initialization voltage line and the second initialization voltage line are in the same layer as the first gate metal layer; or,
the first initialization voltage line and the second initialization voltage line are in the same layer as the second gate metal layer; or,
one of the first initialization voltage line and the second initialization voltage line is in the same layer as the first gate metal layer, while the other of the first initialization voltage line and the second initialization voltage line is in the same layer as the second gate metal layer.