	US 12,406,605 B2
	Semiconductor device
Atsushi Umezaki, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on May 4, 2023, as Appl. No. 18/312,021.
Application 18/312,021 is a continuation of application No. 17/711,120, filed on Apr. 1, 2022, granted, now 11,682,332.
Application 17/711,120 is a continuation of application No. 16/784,383, filed on Feb. 7, 2020, granted, now 11,295,649, issued on Apr. 5, 2022.
Application 16/784,383 is a continuation of application No. 16/109,857, filed on Aug. 23, 2018, granted, now 10,559,606, issued on Feb. 11, 2020.
Application 16/109,857 is a continuation of application No. 15/350,712, filed on Nov. 14, 2016, granted, now 10,062,717, issued on Aug. 28, 2018.
Application 15/350,712 is a continuation of application No. 14/790,309, filed on Jul. 2, 2015, granted, now 9,508,301, issued on Nov. 29, 2016.
Application 14/790,309 is a continuation of application No. 14/250,623, filed on Apr. 11, 2014, granted, now 9,106,224, issued on Aug. 11, 2015.
Application 14/250,623 is a continuation of application No. 13/468,135, filed on May 10, 2012, granted, now 8,698,551, issued on Apr. 15, 2014.
Claims priority of application No. 2011-108133 (JP), filed on May 13, 2011.
Prior Publication US 2023/0274679 A1, Aug. 31, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 19/18 (2006.01); G09G 3/20 (2006.01); G09G 3/36 (2006.01); G11C 19/28 (2006.01); H03K 3/356 (2006.01); H03K 17/06 (2006.01); H03K 17/081 (2006.01); H03K 19/0185 (2006.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); G02F 1/1368 (2006.01); G02F 1/167 (2019.01); G09G 3/3225 (2016.01); G09G 3/34 (2006.01); H10D 30/67 (2025.01); H10K 59/12 (2023.01)

CPC G09G 3/20 (2013.01) [G09G 3/36 (2013.01); G09G 3/3688 (2013.01); G11C 19/184 (2013.01); G11C 19/28 (2013.01); H03K 3/356 (2013.01); H03K 17/06 (2013.01); H03K 17/08104 (2013.01); H03K 19/018521 (2013.01); H10D 86/40 (2025.01); H10D 86/423 (2025.01); H10D 86/441 (2025.01); H10D 86/481 (2025.01); H10D 86/60 (2025.01); G02F 1/1368 (2013.01); G02F 1/167 (2013.01); G09G 3/3225 (2013.01); G09G 3/344 (2013.01); G09G 3/3648 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0876 (2013.01); G09G 2310/0286 (2013.01); G09G 2320/043 (2013.01); G09G 2330/021 (2013.01); H10D 30/6755 (2025.01); H10K 59/12 (2023.02)]

6 Claims

1. A semiconductor device comprising:

a shift register configured to output a plurality of output signals,

wherein the shift register comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, and a second capacitor,

wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,

wherein one of a source and a drain of the second transistor is electrically connected to the first wiring,

wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor,

wherein the other of the source and a drain of the third transistor is electrically connected to a second wiring,

wherein a first electrode of the first capacitor is electrically connected to the second wiring,

wherein a second electrode of the first capacitor is electrically connected to one of a source and a drain of the fourth transistor,

wherein the other of the source and the drain of the fourth transistor is electrically connected to a third wiring,

wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the second transistor,

wherein the other of the source and the drain of the fifth transistor is electrically connected to the third wiring,

wherein a first electrode of the second capacitor is electrically connected to the gate of the second transistor,

wherein a second electrode of the second capacitor is not electrically connected to a gate of the fifth transistor,

wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the first transistor, and

wherein a gate of the sixth transistor is electrically connected to the gate of the second transistor.