US 12,406,321 B2
Elimination cache
Nigel Poole, West Newton, MA (US); Zilin Ying, San Diego, CA (US); Xuhui Mao, San Diego, CA (US); Vijay Kumar Donthireddy, Bengaluru (IN); and Srihari Babu Alla, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Feb. 27, 2023, as Appl. No. 18/175,480.
Prior Publication US 2024/0289912 A1, Aug. 29, 2024
Int. Cl. G06T 1/20 (2006.01); G06T 1/60 (2006.01)
CPC G06T 1/20 (2013.01) [G06T 1/60 (2013.01)] 30 Claims
OG exemplary drawing
 
1. An apparatus for graphics processing, comprising:
a memory; and
at least one processor coupled to the memory and, based at least in part on information stored in the memory, the at least one processor is configured to:
obtain an indication of at least one state update from at least one command processor (CP) associated with a graphics processor, wherein the at least one state update corresponds to one or more states in a set of states associated with the graphics processor;
determine whether the one or more states are stored in a cache associated with the graphics processor;
store the one or more states in the cache based on a number of register updates associated with at least one register being updated a number of times that exceeds a threshold value, wherein register addresses of the stored one or more states are locked in the cache; and
discard the at least one state update based on a determination that the one or more states are stored in the cache or update the cache based on a determination that the one or more states are not stored in the cache.