US 12,406,186 B2
Conflict-free, stall-free, broadcast network on chip
Andrew Stephen Cassidy, San Jose, CA (US); Rathinakumar Appuswamy, San Jose, CA (US); John Vernon Arthur, Mountain View, CA (US); Jun Sawada, Austin, TX (US); Dharmendra S. Modha, San Jose, CA (US); Michael Vincent DeBole, Poughkeepsie, NY (US); Pallab Datta, San Jose, CA (US); and Tapan Kumar Nayak, San Jose, CA (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Oct. 21, 2020, as Appl. No. 17/076,287.
Prior Publication US 2022/0121951 A1, Apr. 21, 2022
Int. Cl. G06N 3/045 (2023.01); G06N 3/063 (2023.01); G06N 3/084 (2023.01)
CPC G06N 3/084 (2013.01) [G06N 3/045 (2023.01); G06N 3/063 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A neural inference chip comprising:
a plurality of network nodes organized into a grid of two or more dimensions with at least one row and at least one column;
a network on chip interconnecting the plurality of network nodes, the network comprising a pair of directional paths for each row and a pair of directional paths for each column, the paths of each pair having opposite directions and a common end, the common end of each pair of directional paths being disposed at an end of the grid, wherein
the network is configured to accept data at any of the plurality of nodes,
the network is configured to propagate the data along a first of a pair of directional paths from a source node to the common end of the pair of directional paths, the first of the pair of directional paths traversing a subset of the plurality of network nodes, and
the network is configured to propagate the data along a second of the pair of directional paths from the common end of the pair of directional paths to one or more destination nodes responsive to the data being propagated along the first of the pair of directional paths to the common end, the second of the pair of directional paths traversing the subset of the plurality of network nodes.