| CPC G06F 30/398 (2020.01) [G06F 1/12 (2013.01)] | 20 Claims |
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1. A computer-implemented method for timing analysis of three-dimensional integrated circuits (3DICs), comprising:
receiving a circuit design for a 3DIC, the circuit design targeted for implementation on a stacked die comprising a plurality of dies, the circuit design comprising a plurality of portions of the circuit design, each portion of the circuit design targeted for a die from the plurality of dies;
selecting a first portion of the circuit design targeted for implementation on a first die and a second portion of the circuit design targeted for implementation on a second die, the circuit design including a set of nets that cross die boundaries, such that each net of the set of nets includes a first timing node in the first portion of the circuit design and a second timing node in the second portion of the circuit design;
selecting a net from the set of nets that cross die boundaries, the net providing signal to one or more load pins;
for each of a plurality of corners associated with the second die:
determining a plurality of sets of timing values of the net, each set of timing values corresponding to a corner associated with the first die;
determining a worst case slack value for the net based on the plurality of sets of timing values; and
determining a timing adjustment value for each load pin of the net based on aggregate timing values determined from the plurality of sets of timing values; and
adjusting the worst case slack value based on the timing adjustment value for the net to reduce pessimism of the worst case slack value.
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