US 12,406,125 B2
Integrated circuit layout including standard cells and method to form the same
Chien-Hung Chen, Taipei (TW); Ruei-Yau Chen, Pingtung County (TW); Wei-Jen Wang, Tainan (TW); Kun-Yuan Wu, Kaohsiung (TW); Chien-Fu Chen, Miaoli County (TW); and Chen-Hsien Hsu, Hsinchu County (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on Jul. 19, 2022, as Appl. No. 17/868,770.
Application 17/868,770 is a continuation in part of application No. 17/517,642, filed on Nov. 2, 2021, granted, now 12,328,944.
Claims priority of application No. 110135987 (TW), filed on Sep. 28, 2021.
Prior Publication US 2023/0097189 A1, Mar. 30, 2023
Int. Cl. G06F 30/392 (2020.01); G06F 30/30 (2020.01)
CPC G06F 30/392 (2020.01) [G06F 30/30 (2020.01)] 10 Claims
OG exemplary drawing
 
1. An integrated circuit layout, comprising:
a power rail and a ground rail extending in parallel along a first direction; and
a first standard cell and a second standard cell abutted to each other side by side between the power rail and the ground rail, which respectively comprising:
an upper edge, a lower edge, and a well boundary between the upper edge and the lower edge extending in parallel along the first direction;
two active regions of opposite conductivity types at two sides of the well boundary; and
a gate line extending between the upper edge and the lower edge along a second direction and intersecting the two active regions, wherein the first direction and the second direction are perpendicular;
wherein a first cell height between the upper edge and lower edge of the first cell and a second cell height between the upper edge and lower edge of the second standard cell are different, the well boundaries of the first standard cell and the second standard cell are aligned along the first direction.