US 12,406,122 B1
Modifying scan patterns to enable broadcasting a scan enable signal to multiple circuit blocks
Amit Gopal M. Purohit, Bangalore (IN); Denis Martin, Mountain View, CA (US); and Paras Chhabra, Bengaluru (IN)
Assigned to SYNOPSYS, INC., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Oct. 11, 2022, as Appl. No. 17/963,599.
Claims priority of provisional application 63/254,690, filed on Oct. 12, 2021.
Int. Cl. G06F 30/333 (2020.01); G06F 11/263 (2006.01); G06F 11/267 (2006.01); G06F 11/27 (2006.01); G06F 30/20 (2020.01); G06F 30/3308 (2020.01); G06F 30/367 (2020.01); G06F 30/398 (2020.01); H03K 3/011 (2006.01); H03K 3/03 (2006.01); H03K 5/00 (2006.01); H03K 19/01 (2006.01); G06F 11/07 (2006.01); H01L 25/00 (2006.01)
CPC G06F 30/333 (2020.01) [G06F 11/0766 (2013.01); G06F 11/263 (2013.01); G06F 11/267 (2013.01); G06F 11/27 (2013.01); G06F 30/20 (2020.01); G06F 30/3308 (2020.01); G06F 30/367 (2020.01); G06F 30/398 (2020.01); H03K 3/011 (2013.01); H03K 3/03 (2013.01); H03K 5/00 (2013.01); H03K 19/01 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving a first scan pattern to test a first circuit block in an integrated circuit (IC) design and a second scan pattern to test a second circuit block in the IC design, wherein a first length of the first scan pattern is different from a second length of the second scan pattern; and
modifying, by a processor, the first scan pattern, the second scan pattern, or both the first scan pattern and the second scan pattern to make lengths of the first scan pattern and the second scan pattern equal.