US 12,406,121 B2
3D integrated circuit with enhanced debugging capability
Pongstorn Maidee, San Jose, CA (US)
Assigned to Xilinx, Inc., San Jose, CA (US)
Filed by Xilinx, Inc., San Jose, CA (US)
Filed on Jul. 1, 2022, as Appl. No. 17/810,547.
Prior Publication US 2024/0005074 A1, Jan. 4, 2024
Int. Cl. G06F 30/333 (2020.01); G01R 31/28 (2006.01); G01R 31/317 (2006.01); G06F 30/3308 (2020.01); G06F 30/343 (2020.01); G06F 30/367 (2020.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 21/66 (2006.01)
CPC G06F 30/333 (2020.01) [G01R 31/2889 (2013.01); G06F 30/343 (2020.01); G01R 31/31702 (2013.01); G01R 31/31704 (2013.01); G01R 31/31705 (2013.01); G06F 30/3308 (2020.01); G06F 30/367 (2020.01); H01L 21/768 (2013.01); H01L 22/30 (2013.01); H01L 23/528 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A method, comprising:
testing a plurality of layers of a 3-dimensional integrated circuit (3D IC), wherein each layer is subdivided into a plurality of regions, wherein the regions from one layer to another are aligned within stacked columns;
determining which regions of the plurality of layers are operational;
determining a number of operational regions in each stacked column; and
for each stacked column including a number of operational regions exceeding a number of operational regions reserved for user circuitry, designating a selected region of a selected layer of the plurality of layers as a debug region.