US 12,406,120 B2
Multicycle path prediction of reset signals
Baijayanta Ray, Bangalore (IN); Alexander Rabinovitch, Shrewsbury, MA (US); and Manish Shroff, Milford, MA (US)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Sep. 27, 2022, as Appl. No. 17/954,159.
Prior Publication US 2024/0104279 A1, Mar. 28, 2024
Int. Cl. G06F 30/3312 (2020.01); G06F 30/3308 (2020.01); G06F 30/367 (2020.01); G06F 30/373 (2020.01); G06F 30/398 (2020.01)
CPC G06F 30/3312 (2020.01) [G06F 30/3308 (2020.01); G06F 30/367 (2020.01); G06F 30/373 (2020.01); G06F 30/398 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving a circuit design driven by a primary clock signal, the circuit design including reset circuitry and sequential circuitry connected to the reset circuitry,
wherein the circuit design includes a secondary clock signal that is slower than the primary clock signal, and
wherein the reset circuitry generates a reset signal that is a function of the secondary clock signal;
remodeling the secondary clock signal at a transition edge of the primary clock signal;
generating a predicted reset signal subsequent to the reset signal at the transition edge of the primary clock signal; and
emulating an operation of the circuit design based on the predicted reset signal such that the predicted reset signal from the reset circuitry propagates through multiple cycles of the primary clock signal.