US 12,406,119 B2
Processor chip timing adjustment enhancement
Todd A. Christensen, Rochester, MN (US); John E. Sheets, II, Zumbrota, MN (US); Eric Marz, Williston, VT (US); and Kirk D. Peterson, Jericho, VT (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Dec. 3, 2021, as Appl. No. 17/541,797.
Prior Publication US 2023/0177243 A1, Jun. 8, 2023
Int. Cl. G06F 30/3312 (2020.01); G06F 30/3323 (2020.01); G06F 30/398 (2020.01)
CPC G06F 30/3312 (2020.01) [G06F 30/3323 (2020.01); G06F 30/398 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method for improving processor chip timing adjustment in a computing environment, the method comprising:
collecting data relating to one or more components in one or more circuit paths during a design stage of a processor chip based on a design model, wherein each of the one or more components contributes to a time slack comprising a delta value;
adding one or more delta values to the one or more circuit paths of the design model, wherein each added delta value corresponds to collected data relating to the one or more components in the one or more circuit paths;
responsive to adding the one or more delta values to the one or more circuit paths, identifying one or more broken circuit paths; and
adjusting a target time for each of the one or more broken circuit paths.