US 12,406,118 B1
System and method for managing serial lanes in a multi-user emulation system
Barton L. Quayle, San Jose, CA (US); Chi Ming Yeung, Dublin, CA (US); and Choshu Ito, San Mateo, CA (US)
Assigned to Cadence Design Systems, Inc., San Jose, CA (US)
Filed by Cadence Design Systems, Inc., San Jose, CA (US)
Filed on Nov. 29, 2021, as Appl. No. 17/536,559.
Int. Cl. G06F 30/3308 (2020.01); G06F 111/02 (2020.01); G06F 111/20 (2020.01)
CPC G06F 30/3308 (2020.01) [G06F 2111/02 (2020.01); G06F 2111/20 (2020.01)] 16 Claims
OG exemplary drawing
 
1. A computer-implemented method for use with a multi-user emulation system comprising:
providing a plurality of emulation chips having at least one serializer/deserializer (“SERDES”) interconnect therebetween;
emulating, using at least one of the plurality of emulation chips associated with a first domain, a first design;
identifying at least one unused pin associated with the first domain;
allowing access to the at least one unused pin for a second domain during the emulating of the first design;
recognizing the second domain having at least one additional SERDES interconnect associated therewith; and
testing the at least one additional SERDES interconnect prior to emulating the second design.