| CPC G06F 30/327 (2020.01) [G06F 30/392 (2020.01)] | 12 Claims |

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1. A computer-implemented method of extracting parasitic parameters of a 3D IC in a design database, executed by an electronic design automation (EDA) platform installed on a computer architecture, wherein said 3D IC is provided with multiple dies stacked and connected together through hybrid bonding vias, and said method comprises:
merging respective layouts of said multiple dies in said design database into a common layout;
creating a common layout versus schematic (LVS) file and a common layout parameter extraction (LPE) file for said multiple dies in said design database based on said common layout;
creating respective LVS files and respective LPE files for every said die in said design database based on said respective layouts;
creating a common netlist based on said common LVS file and said common LPE file;
creating corresponding respective netlists based on said respective LVS files and said respective LPE files;
merging said common netlist and said respective netlists into a netlist; and
extracting common parasitic parameters of said multiple dies in said design database from said netlist, wherein parasitic parameters at bonding interfaces of said multiple dies in said design database are extracted through said common LPE file.
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