US 12,406,021 B2
Systems and methods for mapping matrix calculations to a matrix multiply accelerator
David Fick, Austin, TX (US); Michael Henry, Austin, TX (US); Laura Fick, Austin, TX (US); Malav Parikh, Austin, TX (US); Skylar Skrzyniarz, Austin, TX (US); Scott Johnson, Austin, TX (US); Pei-Ci Wu, Austin, TX (US); and Andrew Morten, Austin, TX (US)
Assigned to Mythic, Inc., Austin, TX (US)
Filed by Mythic, Inc., Austin, TX (US)
Filed on Mar. 16, 2023, as Appl. No. 18/122,701.
Application 18/122,701 is a continuation of application No. 17/193,339, filed on Mar. 5, 2021, granted, now 11,615,165.
Application 17/193,339 is a continuation of application No. 16/683,515, filed on Nov. 14, 2019, granted, now 10,977,339.
Application 16/683,515 is a continuation of application No. 16/402,090, filed on May 2, 2019, granted, now 10,515,136, issued on Dec. 24, 2019.
Application 16/402,090 is a continuation of application No. 16/392,979, filed on Apr. 24, 2019, granted, now 10,452,745, issued on Oct. 22, 2019.
Application 16/392,979 is a continuation of application No. 16/222,277, filed on Dec. 17, 2018, granted, now 10,409,889, issued on Sep. 10, 2019.
Prior Publication US 2023/0222174 A1, Jul. 13, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 17/16 (2006.01); G06N 20/00 (2019.01)
CPC G06F 17/16 (2013.01) [G06N 20/00 (2019.01)] 18 Claims
OG exemplary drawing
 
1. A method of configuring an integrated circuit with coefficient values, the method comprising:
identifying a coefficient mapping technique based on attributes of two or more computational algorithms;
configuring a plurality of processing circuits of the integrated circuit with coefficient values of the two or more computational algorithms based on the identified coefficient mapping technique,
wherein the identified coefficient mapping technique includes mapping a set of coefficients of a first algorithm of the two or more computational algorithms to a first set of processing circuits of the plurality of processing circuits and mapping a second set of coefficients of a second algorithm of the two or more computational algorithms to a second set of processing circuits of the plurality of processing circuits, and
wherein identifying the coefficient mapping technique is based on identifying that a computation of at least one of the sets of coefficients of the first algorithm and the second algorithm requires fewer outputs than an output capacity of the plurality of processing circuits.