| CPC G06F 15/7814 (2013.01) [G06F 9/30036 (2013.01)] | 3 Claims |

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1. An improved resource-conservative computer processor chip optimized for hypervector algebra to store, process, and losslessly retrieve information comprising:
a process flow module;
a hypervector data embedding module on-chip;
a hypervector instruction encoding module;
a hypervector desaturation module; and,
a hypervector decoding module that is on-chip;
an intelligent self-activation software to monitor when data has been associated together and stored in an on-chip record, wherein the activation software:
sequesters hypervectors that are active in a global memory;
forms suggestions and generalizations of complete datasets from available partial data;
activates sequestered hypervectors by returning them to the global memory; and,
updates the on-chip record continuously.
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