| CPC G06F 13/1694 (2013.01) [G06F 13/1678 (2013.01); G06F 13/1684 (2013.01)] | 23 Claims |
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1. A system comprising:
first and second memory devices having common address and command signals, wherein each memory device has a respective first data width, and wherein the first and second devices are configured to collectively provide a memory interface having a second data width, the second data width having twice as many bits as the first data width; and
a memory controller chiplet includes one or more processors, and is configured to perform memory access operations including a memory read operation comprising issuing read commands to read data from the first and second memory devices using an I/O interface having four memory channels,
wherein the memory controller is configured to issue independent command/address (C/A) commands over each memory channel to access independently addressable regions of each memory device, wherein the C/A commands of a first memory read operation in a first memory channel comprise,
at a first time, providing a first row-activate command to the first memory channel, followed by a first read command, and
at a second time, prior to expiration of an activate-to-activate delay interval initiated with the first row-activate command, providing a second read command to the first memory channel;
wherein the memory controller is further configured to receive data responsive to read requests, including:
at a third time, before the second time, receiving a first burst of data responsive to the first row-activate command and the first read command; and
at a fourth time, after the second time receiving a first burst of data responsive to the first row-activate command and the second read command.
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