US 12,405,899 B1
Innovative way to improve the translation lookaside buffer (TLB) miss latency
Waseem Kraipak, Hyderabad (IN); and Brian Michael Rogers, Durham, NC (US)
Assigned to Marvell Asia Pte Ltd, Singapore (SG)
Filed by Marvell Asia Pte Ltd, Singapore (SG)
Filed on Jan. 27, 2023, as Appl. No. 18/160,971.
Claims priority of provisional application 63/433,375, filed on Dec. 16, 2022.
Int. Cl. G06F 12/10 (2016.01); G06F 12/1027 (2016.01)
CPC G06F 12/1027 (2013.01) [G06F 2212/1024 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of reducing page walk latency resulting from a translation lookaside buffer (TLB) miss, comprising:
providing a page fetch/walk logic module disposed between a coherent fabric and a memory controller, the coherent fabric configured to support a page walk protocol by checking a TLB request message for encoding that indicates the TLB miss, and forwarding the TLB request message when the encoding indicates the TLB miss;
upon receiving a notification of a TLB miss, performing, by the page fetch/walk logic module, a page table walk of a virtual address to produce a corresponding physical address.