US 12,405,891 B2
Graphics processor cache for data from multiple memory spaces
Dimitri Tan, Austin, TX (US); and William V. Miller, Austin, TX (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Feb. 21, 2024, as Appl. No. 18/583,520.
Claims priority of provisional application 63/578,719, filed on Aug. 25, 2023.
Prior Publication US 2025/0068564 A1, Feb. 27, 2025
Int. Cl. G06F 12/08 (2016.01); G06F 12/0811 (2016.01); G06F 12/084 (2016.01); G06T 1/60 (2006.01)
CPC G06F 12/084 (2013.01) [G06F 12/0811 (2013.01); G06T 1/60 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
graphics processor circuitry configured to operate on data in multiple memory address spaces;
data cache circuitry configured to cache data for the graphics processor circuitry, including data from the multiple memory address spaces at a first cache level, wherein the data cache circuitry includes:
tag circuitry configured to compare, from access requests to the first cache level of the data cache circuitry with tags of entries in the data cache circuitry, both:
a tag portion of a requested address, wherein the tag portion of a requested address is included in a first set of address bits for a first space of the multiple memory address spaces and is included in a second set of address bits for a second space of the multiple memory address spaces; and
memory address space information for the requested address, wherein the memory address space information identifies one of the multiple memory address spaces from which data is cached at the first cache level.