US 12,405,866 B2
High performance processor for low-way and high-latency memory instances
Elad Sity, Kfar Saba (IL); and Eliad Hillel, Kfar Saba (IL)
Assigned to NeuroBlade Ltd., Tel Aviv (IL)
Filed by NeuroBlade Ltd., Tel Aviv (IL)
Filed on Jan. 8, 2024, as Appl. No. 18/406,346.
Application 17/397,061 is a division of application No. 16/512,622, filed on Jul. 16, 2019, granted, now 11,126,511, issued on Sep. 21, 2021.
Application 18/406,346 is a continuation of application No. 17/397,061, filed on Aug. 9, 2021, granted, now 11,914,487.
Application 16/512,622 is a continuation of application No. PCT/IB2018/000995, filed on Jul. 30, 2018.
Claims priority of provisional application 62/548,990, filed on Aug. 23, 2017.
Claims priority of provisional application 62/538,722, filed on Jul. 30, 2017.
Claims priority of provisional application 62/538,724, filed on Jul. 30, 2017.
Prior Publication US 2024/0143457 A1, May 2, 2024
Int. Cl. G06F 9/38 (2018.01); G06F 9/30 (2018.01); G06F 11/10 (2006.01); G06F 11/16 (2006.01); G06F 13/16 (2006.01); G06F 15/80 (2006.01); G06N 3/04 (2023.01); G11C 7/10 (2006.01); G11C 11/16 (2006.01); G11C 11/4076 (2006.01); G11C 11/408 (2006.01); G11C 11/4093 (2006.01); G06F 15/76 (2006.01)
CPC G06F 11/1658 (2013.01) [G06F 9/3001 (2013.01); G06F 9/3885 (2013.01); G06F 9/3889 (2013.01); G06F 9/3895 (2013.01); G06F 11/1016 (2013.01); G06F 11/102 (2013.01); G06F 11/16 (2013.01); G06F 11/1616 (2013.01); G06F 13/1657 (2013.01); G06F 15/8038 (2013.01); G06N 3/04 (2013.01); G11C 7/1072 (2013.01); G11C 11/1655 (2013.01); G11C 11/1657 (2013.01); G11C 11/1675 (2013.01); G11C 11/4076 (2013.01); G11C 11/408 (2013.01); G11C 11/4093 (2013.01); G06F 2015/765 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method performed for operating a distributed memory device comprising:
determining a number of words that are required simultaneously to perform a task, the task requiring at least one computation, and
providing instructions for writing words that need to be accessed simultaneously in a plurality of memory banks when a number of words that can be accessed simultaneously from one of the plurality of memory banks is lower than the number of words that are required simultaneously;
receiving, by a configuration manager, an indication to perform the task; and
in response to receiving the indication, configuring a memory controller to:
within a first line access cycle:
access at least one first word from a first memory bank from the plurality of memory banks using a first memory line,
send the at least one first word to at least one processing unit connected to the memory controller, and
open a first memory line in a second memory bank to access a second address from the second memory bank from the plurality of memory banks, and
within a second line access cycle:
access at least one second word from the second memory bank using the first memory line,
send the at least one second word to at least one processing unit connected to the memory controller, and
access a third address from the first memory bank using a second memory line in the first memory bank.