US 12,405,854 B2
Fault-tolerant memory appliance
Mohamad El-Batal, Superior, CO (US); Jon D. Trantham, Chanhassen, MN (US); David Jerome Allen, Longmont, CO (US); Matthew Bruce Lovell, Longmont, CO (US); and Kevin Lee Van Pelt, Longmont, CO (US)
Assigned to SEAGATE TECHNOLOGY LLC, Fremont, CA (US)
Filed by Seagate Technology LLC, Fremont, CA (US)
Filed on Dec. 29, 2023, as Appl. No. 18/400,782.
Claims priority of provisional application 63/478,039, filed on Dec. 30, 2022.
Prior Publication US 2024/0220358 A1, Jul. 4, 2024
Int. Cl. G06F 11/10 (2006.01); G06F 3/06 (2006.01); H04L 67/2876 (2022.01); H04L 67/289 (2022.01)
CPC G06F 11/1044 (2013.01) [G06F 3/0614 (2013.01); H04L 67/2876 (2013.01); H04L 67/289 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A system, comprising:
a first fabric switch configured to receive a stream of data from one of a plurality of clients, the first fabric switch configured to store the stream of data at one of a first set of dual-ported memory modules;
a second fabric switch configured to receive the stream of data from the one of the plurality of clients, the second fabric switch configured to store the stream of data at one of a second set of dual-ported memory modules, wherein the first set of dual-ported memory modules are different from the second set of dual-ported memory modules; and
a buffer module configured to couple commands from the plurality of clients with the first set of dual-ported memory modules and the second set of dual-ported memory modules, wherein the buffer module comprises:
a plurality of caches to store payloads from an aggregator crossbar,
a plurality of DDR subchannels, and
a plurality of DDR arbiters configured to select payload from the plurality of cache and provide the selected payloads to one of the plurality of DDR subchannels; and
wherein each of the first fabric switch and the second fabric switch is configured to dual-cast the stream of data to a paired set of memory modules, the paired set of memory modules including a first memory module from the first set of dual-ported memory modules and a second memory module from the second set of dual-ported memory modules.
 
9. A memory blade, comprising:
a plurality of fabric switches configured to receive commands from a plurality of host clients;
an address decoder and tracker circuit communicatively connected to the fabric switches and configured to determine the source of commands received at the fabric switches;
an aggregator crossbar configured to provide bandwidth aggregation between host clients and a plurality of memory modules; and
a buffer module configured to couple the commands from the plurality of host clients with the plurality of memory modules, wherein the buffer module further comprises:
a plurality of caches to store payloads from the aggregator crossbar;
a plurality of DDR subchannels; and
a plurality of DDR arbiters configured to select payload from the plurality of cache and provide the selected payloads to one of the plurality of DDR subchannels.
 
15. A memory appliance, Comprising:
a first fabric switch configured to receive a stream of data from one of a plurality of clients, the first fabric switch configured to store the stream of data at one of a first set of dual-ported memory modules;
a second fabric switch configured to receive the stream of data from the one of the plurality of clients, the second fabric switch configured to store the stream of data at one of a second set of dual-ported memory modules, wherein the first set of dual-ported memory modules are different from the second set of dual-ported memory modules, wherein each of the first fabric switch and the second fabric switch is configured to dual-cast the stream of data to a paired set of memory modules, the paired set of memory modules including a first memory module from the first set of dual-ported memory modules and a second memory module from the second set of dual-ported memory modules;
an aggregator crossbar configured to provide bandwidth aggregation between the first and the second fabric switch and the first and the second sets of dual-ported memory modules; and
a plurality of arbiters configured to select the payloads from a plurality of caches and couple them to one of a plurality of DDR subchannels.