US 12,405,848 B2
Error correction dynamic method to detect and troubleshoot system boot failures
Ibrahim Sayyed, Georgetown, TX (US); Chris Edward Pepper, Leander, TX (US); Christopher Channing Griffin, Cedar Park, TX (US); Elmira M. Bonab, Austin, TX (US); and Purushothama R. Malluru, Round Rock, TX (US)
Assigned to DELL PRODUCTS L.P., Round Rock, TX (US)
Filed by DELL PRODUCTS L.P., Round Rock, TX (US)
Filed on Oct. 5, 2022, as Appl. No. 17/960,408.
Prior Publication US 2024/0118966 A1, Apr. 11, 2024
Int. Cl. G06F 11/30 (2006.01); G06F 11/07 (2006.01)
CPC G06F 11/0793 (2013.01) [G06F 11/0757 (2013.01); G06F 11/3024 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A data processing system comprising:
a processor having a working non-transient data memory and processing logic;
a boot system configured to load one or more algorithms for initializing a basic input output system (BIOS) of the processor into the working non-transient data memory; and
an error correction system configured to start a first watchdog timer for a pre-boot stage and to monitor initialization of the processor and to store data associated with the first watchdog timer in a non-volatile random access memory, the error correction system further configured to implement a corrective process if the first watchdog timer times out prior to receipt of a predetermined signal and to start a second watchdog timer upon receiving a success signal at an end of each of a plurality of BIOS phases after completion of the pre-boot phase and to store data associated with the second watchdog timer in the non-volatile random access memory.