| CPC G06F 9/52 (2013.01) | 11 Claims |

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1. An apparatus for synchronizing participants of a simulation of a chip design partitioned into parts, the apparatus comprising:
a plurality of partitions, each partition being configured to run a respective simulation participant independently from other simulation participants;
a backplane connecting the plurality of partitions and being configured to transfer data between the plurality of partitions, the data including time stamps indicating a partition time of a simulation participant on at least one partition; and
a synchronizer configured to synchronize the multiple partitions by stopping the running simulation participant of the at least one partition, when a time stamp of the running simulation participant is outside a synchronization window,
wherein the synchronization window has a predetermined time length indicating a range of acceptable time stamps and starts with a time associated with a time stamp of a slowest running simulation participant;
wherein the synchronizer is configured to issue an approval of a request for updating a simulation time of a simulation participant, when the updated simulation time is inside the synchronization window;
wherein all partitions are connected to the synchronizer which is configured to control the simulation time in all partitions;
wherein each partition comprises a scheduler, the scheduler being configured to schedule jobs of the respective simulation participant based on time stamps independently from other simulation participants; and
wherein the synchronizer is configured to allow the scheduler of the partitions to freely schedule the jobs as long as the time stamps are inside the synchronization window.
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