US 12,405,823 B2
Resource sharing by two or more heterogeneous processing cores
Sharan Ashwathnarayan, Bangalore (IN); Debalina Bhattacharjee, Bangalore (IN); Ashok Kelur, Santa Clara, CA (US); Alok Parikh, Bangalore (IN); Yogesh Kini, Bangalore (IN); Amit Rao, Bangalore (IN); Aingarathasan Paramakuru, Pickering (CA); Kathleen E. Danielson, San Francisco, CA (US); Daniel Jonathan Hettena, Princeton, NJ (US); and Vladislav Buzov, San Ramon, CA (US)
Assigned to NVIDIA Corporation, Sunnyvale, CA (US)
Filed by NVIDIA Corporation, Santa Clara, CA (US)
Filed on Nov. 8, 2019, as Appl. No. 16/679,082.
Claims priority of application No. 201911019475 (IN), filed on May 16, 2019.
Prior Publication US 2020/0364088 A1, Nov. 19, 2020
Int. Cl. G06F 9/50 (2006.01); G06F 9/48 (2006.01); G06F 9/52 (2006.01)
CPC G06F 9/5016 (2013.01) [G06F 9/48 (2013.01); G06F 9/4806 (2013.01); G06F 9/4843 (2013.01); G06F 9/4881 (2013.01); G06F 9/50 (2013.01); G06F 9/5005 (2013.01); G06F 9/5027 (2013.01); G06F 9/5033 (2013.01); G06F 9/5044 (2013.01); G06F 9/505 (2013.01); G06F 9/5088 (2013.01); G06F 9/52 (2013.01); G06F 9/522 (2013.01); G06F 9/526 (2013.01)] 65 Claims
OG exemplary drawing
 
1. A processor, comprising: one or more circuits to perform one or more application programming interfaces (APIs) to cause different types of memory to be allocated to at least two heterogeneous processing cores based, at least in part, on one or more different attributes associated with the at least two heterogeneous processing cores.