| CPC G06F 9/455 (2013.01) [G06F 11/3648 (2013.01)] | 9 Claims |
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1. A hardware mapping method of a computer device comprising at least one processor, the hardware mapping method comprising:
receiving, by the at least one processor, model software of a generative artificial intelligence model including a large language model (LLM);
receiving, by the at least one processor, information on an existing hardware structure; and
sequentially performing, by the at least one processor, source code level simulation, instruction level simulation, and register transfer level simulation for the model software,
wherein the performing comprises:
cross-verifying an instruction written with the source code level simulation through the instruction level simulation,
determining whether implementation of the model software is possible with the existing hardware structure after performing the source code level simulation and performing the cross-verifying before performing the register transfer level simulation;
adding a hardware module to the existing hardware structure when the implementation is impossible; and
reperforming the instruction level simulation for verifying the instruction,
wherein the adding and the reperforming are repeated until the implementation of the model software is determined to be possible with the hardware structure including the added hardware module, and
wherein the performing further comprises:
writing a module-level test case for each instruction cross-verified through the source code level simulation and the instruction level simulation; and
verifying at least one of the written test cases through the register transfer level simulation.
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