US 12,405,803 B1
Superscalar execution using pipelines that support different precisions
Christopher A. Burns, Austin, TX (US); and Liang-Kai Wang, Austin, TX (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Nov. 2, 2022, as Appl. No. 18/052,000.
Claims priority of provisional application 63/376,007, filed on Sep. 16, 2022.
Int. Cl. G06F 9/38 (2018.01); G06F 7/499 (2006.01); G06F 7/544 (2006.01); G06F 9/30 (2018.01)
CPC G06F 9/3867 (2013.01) [G06F 7/49947 (2013.01); G06F 7/5443 (2013.01); G06F 9/3001 (2013.01); G06F 9/3836 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
pipeline circuitry that includes multiple pipelines, including:
a first pipeline configured to execute a first type of operation on operands having up to a first precision; and
a second pipeline configured to execute the first type of operation on operands having up to a second precision that is greater than the first precision;
scheduling circuitry configured to select operations for issuance to the multiple pipelines, for a given cycle from multiple ready threads, including to:
prioritize a determined highest-precision operation of the first type from ready operations; and
assign the determined operation to a lowest-precision pipeline, of the multiple pipelines, that is configured to perform the first type of operation according to the operand precision of the determined operation.