US 12,405,802 B2
Methods and systems for inter-pipeline data hazard avoidance
Luca Iuliano, Chesham (GB); Simon Nield, Wendover (GB); Yoong-Chert Foo, London (GB); and Ollie Mower, Harrow (GB)
Assigned to Imagination Technologies Limited, Kings Langley (GB)
Filed by Imagination Technologies Limited, Kings Langley (GB)
Filed on Feb. 12, 2024, as Appl. No. 18/439,700.
Application 18/439,700 is a continuation of application No. 18/220,048, filed on Jul. 10, 2023, granted, now 11,900,122.
Prior Publication US 2025/0021340 A1, Jan. 16, 2025
Int. Cl. G06F 9/22 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/3861 (2013.01) [G06F 9/3016 (2013.01); G06F 9/3834 (2013.01); G06F 9/3838 (2013.01); G06F 9/3867 (2013.01); G06F 9/3889 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of processing instructions in a parallel processing unit comprising a plurality of instruction pipelines, the method comprising:
tracking data hazards using a plurality of counters, the plurality of counters comprising a first set of counters associated with high latency data hazards and a second set of counters associated with low latency data hazards;
receiving an instruction for execution that indicates (i) whether the instruction is a secondary instruction that depends on at least one primary instruction, and (ii) if the instruction is a secondary instruction, a counter of the plurality of counters associated with each primary instruction from which the instruction depends;
determining whether the instruction is a secondary instruction;
in response to determining that the instruction is a secondary instruction, analysing the counter associated with each primary instruction from which the instruction depends to determine whether the instruction relates to at least one high latency data hazard that has not been resolved;
in response to determining that the instruction relates to at least one high latency data hazard that has not been resolved, causing the instruction to be de-scheduled until each high latency data hazard related to the instruction has been resolved; and
in response to determining that the instruction does not relate to at least one high latency data hazard that has not been resolved, forwarding the instruction to a queue preceding an appropriate instruction pipeline of the plurality of instruction pipelines where the instruction stalls until all low latency data hazards related to the instruction have been resolved.