US 12,405,801 B2
Scalarization of instructions for SIMT architectures
Aditya Avinash Atluri, Redmond, WA (US); Jack Choquette, Palo Alto, CA (US); Carter Edwards, Campbell, CA (US); Olivier Giroux, Santa Clara, CA (US); Praveen Kumar Kaushik, Bengaluru (IN); Ronny Krashinsky, Portola Valley, CA (US); Rishkul Kulkarni, Austin, TX (US); and Konstantinos Kyriakopoulos, Weinsberg (DE)
Assigned to NVIDIA Corporation, Santa Clara, CA (US)
Filed by NVIDIA Corporation, Santa Clara, CA (US)
Filed on Feb. 3, 2023, as Appl. No. 18/105,679.
Claims priority of application No. 20220100820 (GR), filed on Oct. 6, 2022.
Prior Publication US 2024/0118899 A1, Apr. 11, 2024
Int. Cl. G06F 9/38 (2018.01)
CPC G06F 9/3851 (2013.01) 20 Claims
OG exemplary drawing
 
19. A method comprising:
copying a same operand value associated with a set of one or more threads from a private register to a shared register to obtain a shared source operand; and
executing, using a serial execution unit, an instruction associated with the set of one or more threads based at least on the same operand value being associated with the set of one or more threads.